View CXA3271AGE_2004228.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1 ? e00y20-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA3271AGE 30 pin llga (plastic) description the CXA3271AGE is an electrostatic capacitance method fingerprint sensor. this monolithic ic integrates the sensor block, sense amplifier (3-bit gain adjustment), sample-and- hold, output amplifier and output buffer needed to acquire fingerprint images, as well as the timing generator for determining the operation of these functions onto a single chip. features ? electrostatic capacitance type sensor (charge transfer method) number of pixels: 192 128 317 dpi low power consumption (50mw or less) single 3.3v power supply sensor gain control: 3 bits s/n ratio improved by on-chip sensor block parasitic capacitance cancel function applications fingerprint verification units structure silicon gate cmos ic absolute maximum ratings (ta = 25c) supply voltage av dd , dv dd v ss ? 0.5 to +7.0 v input voltage v i v ss ? 0.5 to v dd + 0.5 v output voltage v o v ss ? 0.5 to v dd + 0.5 v operating temperature topr ?20 to +75 c storage temperature tstg ?25 to +125 c allowable power dissipation p d 1100 mw recommended operating conditions supply voltage av dd , dv dd 3.15 to 3.45 v ambient operating temperature ta 0 to +50 c fingerprint sensor
? 2 ? CXA3271AGE block diagram xsp (d/i) clk (d/i) adclk (d/o) uc uc s_cnt c_clk c_sp load r_sp r_clk uc uc uc uc uc uc uc uc uc uc uc di (d/i) aout (a/o) vos (bias) 3 3-bit dac output buffer 192 128 sense amp ( 192) sensor s/h & sw ( 192) row shift register timing generator column shift register ........ 128 ......... ........... 192 ........... 192 192
? 3 ? CXA3271AGE detailed block diagram uc uc uc uc uc uc uc uc uc uc uc uc uc uc uc uc uc sensor (uc) tg mode s3cnt sin, s2n, s11, s11n xsp hd c_clk c_ck r_log dclk sr_s sr_c r_sp s (3:5) n s (3:5) c_sp ........ 128 ......... ........... 192 (dummy) ........... ..................... 192 .................. c_sp c_cout c_log sr_c in_n (1:192) c (1:192) sc (1:192) sc (1:192) n sc (1:192) sc (1:192) n c_co clk xsp samp (192) s (3:5) s (3:5) n sr_s vh, vm, vl dclk r_sp s (6:7) s (6:7) n out oamp in in da vs (1:8) n bias_o vs (3:8) datest vh vm vl dec test (1:2) vh, vm, vl vos s1, s2, s11 datest di (0:2) vs (3:8) sr_c c_cr vs (1:8) n bias_sa av dd (p/s) av ss (p/s) test1 (d/i) test2 (d/i) mode (d/i) di0 (d/i) di1 (d/i) di2 (d/i) xsp (d/i) hd (d/i) clk (d/i) c_clk (d/i) c_ck (d/o) adclk (d/o) rsro (d/o) csro (d/o) dv ss (p/s) dv ss (p/s) dv dd (p/s) vcs_s (bias) vl (bias) vm (bias) vh (bias) vos (bias) vcs_o (bias) aout (a/o) av ss (p/s) av dd (p/s) pin symbol 2c 2d 2e 2f 3b 3c 3d 3e 3f 4b 4c 4d 4e 4f 5f 5e 5d 5c 5b 6f 6e 6d 6c 6b 7f 7e 7d 7c land no. 8 7 6 5 4 3 2 15 14 13 12 11 10 9 1 buf 16 23 22 21 26 25 24 28 27 20 19 18 17 dseln dselg 2 xsp s3cnt da amp vos amp out out vcs_s bias_ref vcs_s c_clk sr (1:128) n sr (1:128) n sr (1:192) sr (1:192) vos vcs_o vcs_o 3 8 6 128 128 192 192 192
? 4 ? CXA3271AGE pin description serial no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 19 18 17 16 15 24 23 22 21 20 28 27 26 25 2b 2c 2d 2e 2f 3b 3c 3d 3e 3f 4b 4c 4d 4e 4f 5b 5c 5d 5e 5f 6b 6c 6d 6e 6f 7b 7c 7d 7e 7f sub av dd av ss test1 test2 mode di0 di1 di2 xsp hd clk c_clk c_ck adclk dv dd dv ss dv ss csro rsro vos vh vm vl vcs_s sub av dd av ss aout vcs_o power power power d/i d/i d/i d/i d/i d/i d/i d/i d/i d/i d/o d/o power power power d/o d/o a/o a/o a/o a/o a/o power power power a/o a/o substrate electrode (chip rear surface electrode) 3.3v. analog power supply 3.3v. analog gnd. test mode selection. connect to gnd. test mode selection. connect to gnd. connect to gnd. gain setting input. (lsb) gain setting input. gain setting input. (msb) sense start pulse input (negative pulse). the column and row shift registers and the timing generator are cleared by this signal. connect to gnd. main clock. (1 to 2mhz) column shift register clock. connect to c_ck (4e). column shift register clock output. connect to c_clk (4d). outputs the internally delayed input clock. digital power supply 3.3v. digital gnd. digital gnd. column shift register final output. (connection is not required.) row shift register final output. (connection is not required.) output amplifier reference voltage monitor. (1.65v) sensor charge voltage monitor. (1 lsb = 80mv) adjustable within the range of 1.92 to 2.48v by the three bits di[0:2]. sense amplifier reference voltage monitor. (1.85v) dummy cell charge voltage monitor for canceling parasitic capacitance. vl = 2vm ? vh sense amplifier current source bias monitor. (do not connect.) substrate electrode (chip rear surface electrode) 3.3v. analog power supply 3.3v. analog gnd. sensor output. output amplifier and output buffer current source bias monitor. (do not connect.) land no. symbol i/o description
? 5 ? CXA3271AGE electrical characteristics 1. dc characteristics (vss = 0v, ta = 25 c) 2. ac characteristics (v dd = 3.3v, v ss = 0v, ta = 25 c) symbol av dd dv dd v ih v il v ih v il i l vh vh vl vl vm vos i dd item analog supply voltage digital supply voltage input voltage (high) input voltage (low) output voltage (high) cmos output voltage (low) cmos input leak current output voltage output voltage output voltage output voltage output voltage output voltage current consumption conditions cmos input cell cmos input cell v dd = 3.3v, i oh = ? 800a v dd = 3.3v, i ol = 2.4ma v dd = 3.3v, cmos input pin (3.3v/0v) v dd = 3.3v (d0 d1 d2) = (l l l) v dd = 3.3v (d0 d1 d2) = (h h h) v dd = 3.3v (d0 d1 d2) = (l l l) v dd = 3.3v (d0 d1 d2) = (h h h) v dd = 3.3v (d0 d1 d2) = ( ? ? ? ) v dd = 3.3v (d0 d1 d2) = ( ? ? ? ) v dd = 3.3v min. 3.15 3.15 0.7v dd vss 2.8 0 ? 5 1.75 1.55 5 ty p. 3.3 3.3 1.92 2.48 1.76 1.2 1.84 1.65 7.5 max. 3.45 3.45 v dd 0.3v dd 3.3 0.4 5 1.92 1.75 11 unit v v v v v v a v v v v v v ma symbol item clock input period number of sensor defects output voltage air level output voltage water level applicable pins clk aout aout min. 400 1000 250 typ. max. 5 1550 450 unit ns defects mv mv conditions ? 1 ? 2 ? 1 output voltage air level means the output level in the condition where nothing is placed against the sensor surface (in other words, in air). this rating value is obtained by measuring 32 points within one line of the sensor output and then taking the average. the gain setting for this measurement is (011). ? 2 output voltage water level specifies the degree to which the output level changes from the air level when a drop of water is placed on the sensor surface. however, it is unrealistic to place a drop of water on each sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level when a drop of water is placed on the surface) are built into the sensor chip, and the average of these output values is calculated. the difference from the air level noted above becomes the water level. the gain setting for this measurement is (011).
? 6 ? CXA3271AGE electrical characteristics measurement circuit 27 25 23 21 19 17 15 13 11 9 7 5 3 1 28 26 24 22 20 18 16 14 12 10 8 6 4 2 digital input pin digital output pin analog output pin av dd aout/o vos/o vm/o vcs_s/o 0.1f 0.1f 0.1f dv ss csro/o adclk/o c_clk/i hd/i di2/i di0/i test2/i av ss av ss vcs_o/o vh/o vl/o dv dd dv ss rsro/o c_ck/o clk/i xsp/i di1/i mode/i test1/i av dd 1.0f vcc 3.3v 1.0f 0.1f 30pf or more is added to each pin. s1
? 7 ? CXA3271AGE application circuit microcomputer dram during registration during verification 8-bit a/d asic binary value, verification verification results fingerprint sensor chip flash registered data application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 8 ? CXA3271AGE description of operation fingerprint sensor principle the principle of this newly developed fingerprint sensor is described below (fig. 1). the sensor block contains an array of metal electrodes which are covered on top by an insulating film (overcoat). when a finger (which is conductive matter) is placed directly against this surface, the three elements of the metal electrode, the insulating film and the finger form a capacitor. the difference between the fingerprint ridges and valleys is the difference in distance to the metal electrodes, and becomes the difference in the capacitance values of the individually formed capacitors. (the ridge capacitance values are determined by the dielectric constant of the insulating film, but the valleys contain air in addition to this, making the difference between the ridge and valley capacitance values even greater than the difference in distance.) using this principle, by applying a constant voltage to all metal electrodes, the charge level accumulated in each electrode differs, making it possible to output the unevenness of the fingerprint as an electric signal by transferring and converting these charges to voltages. ridge valley fingerprint unevenness overcoat metal electrode inter-layer film si fig. 1
? 9 ? CXA3271AGE sr s4 s3 cf1 cf2 s6 s7 s11 s2 vl vm s1 vh sense amplifier block (192) output block (1) sensor block (192 128) s5 sc cs cp cp' vcel vsl s_amp o_amp vos ch2 ch1 voi voo buf aout vdmy vsns fig. 2 fingerprint sensor operation (fig. 2) description of characters cs: capacitance formed between the finger and the metal electrode cp: parasitic capacitance formed between the metal electrode and the silicon substrate cp': capacitance for canceling cp (cp cp') ch ? : hold capacitance cf ? : feedback capacitance for determining the gain s ? : switch v ? : node voltage vh ? vm vm ? vl detailed description of operation (all switches are off in the default status.) 1. s1, s4 and sr are turned on, and vcel is set to voltage vh. vcel accumulated charge (cs + cp) vh 2. s1 and sr are turned off. 3. s11 and s3 are turned on, and vdmy is set to voltage vl. vdmy accumulated charge cp ? vl 4. s3 and s11 are set to off. 5. s2 is turned on and vsl is set to vm. 6. s4 is turned off. 7. sr, s3 and s5 are turned on. at this time, the charge level that moves from vcel and vdmy to vsl (actually between capacitances) is: (cs + cp) (vh ? vm) ? cp' (vm ? vl) cs (vh ? vm) this means that the sense amplifier gain is determined independently of the parasitic capacitance, making it possible to obtain the required large signal dynamic range. vsns = vm ? cs (vh ? vm)/cf1 the voltage vsns determined as shown above is accumulated in ch1. 8. s5 is turned off. 9. s6 is turned on and the voi voltage is set to vos. 10. s6 is turned off. 11. sc and s7 are turned on. at this time, the charge level that moves from ch1 to cf2 is: (vos ? vsns) ch1 this determines the voo voltage which is accumulated in ch2 and output to aout via the buffer.
? 10 ? CXA3271AGE appearance and readout order 15.36mm 19.8mm sensor area 192 128 scan formation cell (1, 1) to cell (1, 192) cell (128, 1) to cell (128, 192) 16.8mm flip 10.24mm cell (1, 1) cell (128, 1) cell (1, 192) cell (128, 192) g f e d c b a 1234 7 6 58
? 11 ? CXA3271AGE notes on operation sr s4 s3 cf1 cf2 s6 s7 s5 sc cs cp cp' vcel vsl s_amp o_amp vos ch2 ch1 voi voo buf aout vdmy vsns s11 s2 vl vm s1 vh aout output variance aout output variance can be broadly classified into two types. the first is variance intrinsic to the ic, and the second is variance caused by the influence of external noise due to the extremely high sensitivity. variance intrinsic to the ic 1. the aout output dc level fluctuates widely due to the ic. this is caused by the cp and cp' capacitance values, the vm voltage level, the voltage differences vh ? vm and vm ? vl, and the vos voltage level in the figure above. vos, vh, vm and vl appear externally as pins. the aout output level can be set to the desired potential by applying the vos voltage from an external source. the aout dynamic range is approximately 0.6 to 2.1v, so checking this output level and externally applying the vos voltage to set the optimum level is recommended. 2. 192 variances within one line one line is comprised of 192 sensors. each sensor is connected to a separate s_amp, so the s_amp offset appears in the output. (approximately 100 to 200mv) 3. the dc level of a line changes with a certain regularity for some ics. this is also caused by the s_amp dc offset. variance due to the influence of external noise 1. output fluctuation due to cross talk from the power supply power supply fluctuation has a large influence on the aout output of this ic. in addition to the capacitances between the power supply and gnd (approximately 1f, both sides if possible), attaching capacitances of approximately 0.1f to vos, vh, vm and vl is recommended. 2. finger stabilization the human body acts as an antenna, so the finger potential changes during the sensing period, producing noise in the aout output. to prevent this, the potential of the area around the finger being sensed must be equalized with the sensor gnd. measures such as placing a metal plate connected to gnd around the sensor so that the finger touches this place during sensing are recommended.
? 12 ? CXA3271AGE fingerprint sensors have the silicon chip directly exposed, so care should be taken for the following points. in addition, a cover should be attached to protect the sensor surface during operation. sensor surface electrostatic strength contact discharge (150pf, 330 ? ): 1.25kv or more body charge (when the charge accumulated in the body is discharged over the sensor surface): 4kv or more body charge differs between individuals. sensor surface strength the sensor surface is covered with only a thin coating in order to acquire fingerprint information. therefore, care should be taken when handling the sensor. problems have been confirmed not to occur during the following tests. pressing 10,000 times with a finger (pressing time: 2s/time) rubbing 10,000 times with a finger (back and forth, 2s/time) scratching with a fingernail (20 times back and forth) rubbing strongly with a pencil (6h hardness) (20 times back and forth) rubbing with a tissue (1,000 times back and forth) note that problems also occurred with the sensor surface during the following tests. pressing strongly with a needle (normal sewing needle) rubbing with an eraser rubbing with the tip of a ball point pen rubbing with steel wool
? 13 ? CXA3271AGE timing chart 500ns xsp (3f) clk (4c) strobe point input level v ih = 0.7v dd v il = 0.3v dd 0.65v dd 0.35v dd output level 250ns 250ns 250ns 480ns high x low
? 14 ? CXA3271AGE input/output signal clk (4c) input xsp (3f) input strobe point (ck rise + 480ns) 500ns (1clk) 250ns 750ns 750ns ck1 clock 2mhz f = 2.0mhz aout (7e) output aout (7e) detail (repeat 128 times) 96s (192clk) 1st culumn 32s (64clk) 96s (192clk) 2nd culumn 32s (64clk) dynamic range average analog output analog output air level 1.0 to 1.55v 2.1v 0.6v 256.5s (513clk) ((192 + 1 + 63) 2 + 1) 500ns (1clk)
? 15 ? CXA3271AGE sony code eiaj code jedec code package material terminal treatment terminal material package mass organic substrate copper plating llga-30p-01 gold plating 30pin llga (plastic) 0.7 g package structure 52- 1.2 0.08 a b c d e f g 123 45 6 7 8 3- 2.2 2.3 2.2 2.2 2.07 2.07 2.3 3.65 2.54 0.1 s a b m 2.54 3.42 b a x 0.25max 0.25max detail y typ typ sensor area pin1 index 20 17 0.2 sa m 0.15 0.2 s b m ? 12.64 0.25 ? 2.6 0.25 (10.04) ? 2.42 0.25 (15.16) y ? 17.58 0.25 4-r1.0max (0.85) detail x 1.45 0.2 0.05max 0.1 s s 0.2 0.2 note2: the length of breedout is 0.25max. breedout of sensor area. note1: dimension " ? " does not include package outline unit: mm sony corporation

▲Up To Search▲

Price & Availability of CXA3271AGE

	To Download CXA3271AGE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .